PA-RISC information - since 1999

Convex Exemplar SPP1000, SPP1200, SPP1600

Quick Facts
Introduced 1994-1996
Period Maturity (III)
Series Mainframe
CPU 2-16 (CD)/2-8 (XA)
PA-7100/
PA-7200
100-120 MHz
Caches 512 KB-2 MB L1
RAM 4 GB (CD)
2 GB (XA)
Design Crossbar
Drives 20 SCSI
Expansion 16 SBus (CD)
8 SBus (XA)
Bandwidth CPU/Mem 1 GB/s
I/O 250 MB/s
XBAR 1.25 GB/s
SCI 2.4 GB/s
I/O SCSI
Console
SCI/CTI links (XA)

The Convex Exemplar SPP1000, SPP1200 and SPP1600 are scalable 32-bit PA-RISC mainframes with HP PA-7100 or PA-7200 processors, released by Convex in 1994. Previous Convex designs used custom Convex processors, with the SPP mainframes, Convex switched to HP PA-RISC CPUs.

Around the early 1990s, Convex and HP started collaborating more closely, from joint cluster-computing solutions based on HP 9000 in 1992, HP licensing HP-UX to Convex in 1993 and finally in HP becoming a value-added reseller (VAR) for Convex before acquiring the company outright in 1995. The SPP1200 were quickly taken over into the HP product portfolio, before the jointly developed Exemplar SPP2000 was a plain HP product (by the Exemplar division).

Development peaked with the HP 9000 V-Class servers based on Exemplar architecture, with the 64-bit non-clusterable HP 9000/V2200 and V2250 and the up to four-way clusterable HP 9000/V2500 and V2600.

Convex SPP1000, SPP1200 and SPP1600 were available in different types: the CD Compact Design, XA eXtended Architecture hypernodes and XA clusters.

The internal Exemplar architecture is based on a 5x5 crossbar with central internal switching component, the crossbar, connecting resources to each other by forming matrix connections between input and output ports. 5x5 because the crossbar has five ports for processors, memory and I/O.

Nodes and Clusters are controlled and booted by a separate workstation, often a IBM RS/6000 workstation with AIX. This workstation was the Exemplar’s console and control I/O, in a cluster only one node had a control workstation. HP 9000/715 workstations were also used as teststation.

Model Introduced Price
SPP1000/CD 1994 $145,000-$750,000
SPP1000/XA 1994 $550,000-$8 million
SPP1200/CD 1995 $160,000
SPP1200/XA 1995 $586,000
SPP1600 1996

System architecture

Processors

The PA-7100 sported an unusual 2MB expanded primary cache
Model CPU Speed L1 Cache
SPP1000/CD Compact 2-16 PA-7100 100 MHz 2 MB off-chip
SPP1000/XA Hypernode 2-8 PA-7100 100 MHz 2 MB off-chip
SPP1000/XA Cluster 8-128 PA-7100 100 MHz 2 MB off-chip
SPP1200/CD Compact 2-16 PA-7200 120 MHz 512 KB off-chip
SPP1200/XA Hypernode 2-8 PA-7200 120 MHz 512 KB off-chip
SPP1200/XA Cluster 8-128 PA-7200 120 MHz 512 KB off-chip
SPP1600/CD Compact 2-16 PA-7200 120 MHz 1 MB off-chip
SPP1600/XA Hypernode 2-8 PA-7200 120 MHz 1 MB off-chip
SPP1600/XA Cluster 8-128 PA-7200 120 MHz 1 MB off-chip

It is not quite clear how the CD models relate to the XA models — the XA clusters consist of several 2-8 processor hypernodes while the CD models were shipped with up to 16 processors. Either the CDs are different machines than the XA hypernodes or they are simply two XA hypernodes coupled together, without any additional SCI/CTI expansion possibilities.

Chipset

The chipset is based completely on an own Convex design and centers around the Convex five-port crossbar, later improved on the SPP2000 with eight ports and used in HP’s V-Class.

  1. 5x5 nonblocking crossbar, with five crossbar ports, is the central part of the system, it connects to four functional units (memory, SCI links and processor) and with the fifth port to the local system I/O. The four functional units contain each a memory controller, SCI controller and an agent for two processors. Memory and processor use different data links to the crossbar — memory access always goes over the crossbar, even from a processor to the memory in the same functional unit. Each crossbar port has a data rate of 250 MB/s, giving the crossbar a combined peak bandwidth of 1.25 GB/s. The crossbar is implemented in Gallium arsenide gate arrays, GaAs with 250K transistors, a rarity, very expensive and difficult to handle.
  2. Four CPU Agents attach to the crossbar and provide access for the processors to the memory via the crossbar over a 250 MB/s crossbar port shared with the memory controller.
  3. Four Convex Coherent Memory Controllers CCMCs attach each one four-way interleaved memory board to the crossbar. The CCMCs additionally do cache coherency and interface to the Convex’s SCI (CTI) link for inter-hypernode connection. The CTI interface or the complete CCMC were apparently also GaA chips.
  4. Exemplar I/O subsystem connects to the fifth 250 MB/s crossbar port and attaches the I/O subsystem controllers to the crossbar and this memory and processors.

» View a system-level ASCII illustration of the crossbar architecture.

System buses

Memory

Expansion slots

Storage

Clustering

Multiple SPP1x00/XA systems can be connected together to form a single large system.

External ports

Operating systems

Benchmarks

Model SPEC92
fp
SPEC95
int
SPEC95
fp
SPEC95
rate, int
SPEC95
rate, fp
SPP1000 3.27 3.98
SPP1200 185
SPP1600 8-CPU: 290
16-CPU: 541
32-CPU: 996
8-CPU: 383
16-CPU: 744
32-CPU: 1444

Dimensions

Model Height Width Depth Weight
SPP1200/XA 71cm 112cm 178cm 404kg
SPP1200/CD 46cm 99cm 89cm 159kg

References

Manuals

Articles

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