PA-RISC information - since 1999

HP 9000 500 FOCUS

Quick Facts
Introduced 1982
Period Infancy (I)
18 MHz
Cache 16 KB L1
Design IOP/MPB
Drives 1 FD
1 HD
Expansion GP-IO
Bandwidth I/O 5.1 MB/s


With Frank McConnell; some parts taken with permission from him.

The HP 9000/500s computers were the early-1980s predecessors of the PA-RISC workstations and the first member of the HP 9000 series. Although already based on a HP 32-bit processor — the FOCUS — they did not have PA-RISC CPUs yet, which were developed only later.

The HP 9000/520, originally 9020, the first HP 9000 series, was introduced in 1982 by HP and one year later described in the Hewlett Packard Journal as the new HP 9000 computer, a mainframe on the desktop. All 500s used the same HP FOCUS processor, memory and I/O; differences were in casing, expandability and built-in I/O.

The HP 9000/500 series was phased out in the late 1980s, probably due to the complexity and cost of its architecture and was replaced by HP PA-RISC (700/800 series) and M68K (300/400 series) running HP-UX. The first PA-RISC NMOS implementation had one third the amount of FETs of the FOCUS processor and was a much more streamlined design.

HP 9000/520, 530, 540 and 550 introduction dates and prices
Model Introduced Price
520 1982 $30,000
530 1982 $23,105
540 1982 $24,115
550 1984

The HP 9000 520 was used widely by the US Navy from the mid-1980s under the DTC program as a desktop computer for a variety of tactical uses. Originally called Desk-Top Computer (DTC) in 1982, later becoming Desktop Tactical Computer (DTC-1), the program looked at using commercial COTS desktop computers for tactical decision support in US Navy facilities and ships. After evaluation throughout the Navy, the contract was awarded to HP, after which the 9020C version (520 workstation with 13" monitor) became widely deployed throughout the Navy.

About the Joint Operational Tactical System, JTOS, of which the 9020C was an integral part, from the HP Computer Museum (Bill Reed article):

"Despite the fact that some naval leaders didn't see the point of JOTS, at one time, almost every tactical or fleet staff in the United States Navy had five or more HP 9000s, often networked together. Some had the early projection systems for common displays. There was a sharing of the load, so to speak. The computers gave those that processed anti-submarine warfare what they wanted on one terminal while those involved with anti-air warfare processed on another computer. The technology that ensued included special interface boards capturing radar systems, communications systems and aircraft systems, many connected with fiber optics."

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Four distinct models were introduced between 1982 and 1984, based on the same architecture:

HP 9000/520 Dawn, also called HP 9020

HP 9000/530 Corona, also called HP 9030:

HP 9000/540 Corona, also called HP 9040:

HP 9000/550 Shuttle, also called HP 9050:

HP 9000/500s in SMP configuration were also called 600 series (some of the 1980s’ 800s server systems were also called 600 series for a short time).

Possible I/O and expansion options for the 500s:

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The basic architecture of the 500 series was Hewlett-Packard FOCUS, implemented in five NMOS-III VLSI chips fabbed in 1.5 micron: the CPU chip, I/O processor (IOP), memory controller, 128Kb RAM (16 KB cache) and clock driver.

The CPU ran at 18 MHz and had a direct address range of 500 MB (probably 29-bit direct addressing for 512 MB). It was fabricated with 450,000 FETs, integrated with three Floating-Point chips onto one finstrate CPU board. The FOCUS CPU was microcoded with 9,000 38-bit microcode control stores and implemented the HP 3000 computers’ stack-based architecture in 32-bit. All internal data paths and registers are 32-bit wide. Due to heat dissipation difficulties the ICs were mounted on special printed-circuit boards called finstrates — the board has a 1mm copper sheet as core to which the IC substrate is epoxied directly.

The I/O Processor IOP executes all I/O instructions and handles the transactions from/to the eight attached HP CIO channels. It has an I/O bandwith of 5.1 MB/s burst and 973 KB/s multiplexed. The IOP was also a microprogrammed (4,608 32-bit microcode stores) NMOS-III VLSI chip.

At least one IOP to interface with the I/O buses was needed so up to six CPUs were supported in hardware but only three in software. Up to two additional IOPs could be installed for more I/O options; each additional IOP needed an I/O expander which provided the I/O channels extension, the CIO bus.

The three finstrates boards of CPU, IOP and 256 KB RAM were installed in a 12-slot HP 9000/520 module. This allowed configurations of up to 10 MB of RAM; memory cards could be substituted to construct multiprocessor systems. The CPU, IOP and memory controller communicated via the memory processor bus MPB. The 44-line, 18 MHz, 36 MB/s MPB supports up to seven (other sources mention three/three) CPUs or IOPs and fifteen memory controllers.

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The FOCUS is a stack architecture, with 230 instructions (both 32 bits and 16 bits wide), a segmented memory model, and no general purpose programmer-visible registers. There are thirty-nine 32-bit registers in the CPU hardware — thirty-one internal 32-bit general purpose registers, two 32-bit ALU registers, and others.

It has a flat address space but that is not really what most programs see: their access to memory is largely described by registers that contain the absolute memory addresses of segment boundaries. For example, instructions come from the current code segment, which is described by three registers: P, the program counter, which is a 32-bit register containing the absolute address of the instruction being executed; PB, the program base register, which is a 32-bit register containing the absolute address of the first word of the current code segment; and PL, the program limit register, which is a 32-bit register containing the absolute address of the last word of the current code segment.

The data segment also has base (DB) and limit (DL) registers, and so does the stack segment (SB, SL). The stack segment also has a stack pointer (S) and a stack marker pointer (Q) which points to the current procedure’s activation record on the stack.

There is also an index register, a status register, a flags register (really a sort of debugging-state register), a message register (interrupting conditions) and message mask register (which enables/disables interrupts from the message register), a breakpoint register, and a couple of registers which are for the memory controllers to talk to the CPU.

The machine instruction set is oriented toward moving words between memory and the top of the stack, and operating on the words at the top of the stack. To take an addition of two numbers: load one, load the other, execute an ADD instruction, and then a store instruction if the result should be kept somewhere in memory other than on the stack.

The stack is in memory, there are (probably) some numbers of top of stack registers inside the processor to keep things moving relatively quickly, but these registers are not otherwise visible to the programmer.

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A choice of operating systems was provided by HP for the 520: HP BASIC or HP-UX. The 530, 540 and 550 only supported HP-UX. HP-UX ran until version 5.3 on HP FOCUS hardware. The operating systems were built on top of a common kernel, called SUNOS (no relation to Sun Microsystems’ SunOS Unix) which provided basic operating primitives like memory, processor and I/O management. This was intended to be invisible to the user; the Unix operating system on top ran as a single process on it.

There were three revision of SUNOS:




HP-UX for the 9000/500 was the first commercial UNIX supporting a multi-processor, multi-user system.

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