HP 9000 V2200 and V2250
| Quick Facts | |
|---|---|
| Introduced | 1997-1998 |
| Period | Maturity (III) |
| CPU | 4-16 PA-8200 200-240 MHz |
| Caches | 4 MB L1 |
| RAM | 16 GB |
| Design | HyperPlane |
| Drives | 16 SCSI |
| Expansion | 24 PCI |
| Bandwidth | CPU 7.5 GB/s Mem 15 GB/s I/O 1.9 GB/s XBAR 15.3 GB/s |
| I/O | SCSI Console |
Overview
The HP 9000 V2250 and V2250 are large-scale scalable PA-RISC servers, with up to sixteen 64-bit PA-RISC processors in a single cabinet.
They are based on a crossbar architecture — one central internal switching
component links the various computing resources to each other by connecting the devices’ inputs to
other devices’ output ports, in effect forming matrix connections.
The V2200 and V2250 use HP’s own HyperPlane crossbar chipset, consisting of four central
crossbar ASICs and various other chipset components to attach memory, processors and I/O.
The architecture is a direct continuation from the Convex Exemplar — the earlier Convex/HP 32-bit SPP1x00 and 64-bit SPP2000 S-Class/X-Class, use a similar crossbar-based system design. The V2200/V2250 use a very similar design to the SPP2000 S-Class, minus the SCI/TCI links for interconnecting several nodes into a larger syste The V2500/V2600 successors were delivered again with the interconnection technology.
The V2200s and V2250s are controlled via a so-called teststation,
which runs its own HP-UX operating system and controls and monitors the V-Class server.
This teststation is a standard HP 9000/712 workstation
with special teststation hardware, such as a second ethernet and serial boards, and software.
The teststation connects to the Core Utilities Board CUB, which provides booting, system monitoring
and diagnostics, and console connections via one LAN and one special serial link.
System
Processor
- V2200: 4-16 PA-8200 200 MHz with 4 MB off-chip L1 cache each
- V2250: 4-16 PA-8200 240 MHz with 4 MB off-chip L1 cache each
Chipset
The V-Classes are based on the HP HyperPlane crossbar which connects the CPU and I/O to the system main memory.
- HyperPlane crossbar, 8x8, non-blocking, consists of four Exemplar Routing Attachment controllers ERACs
and is the central part of the system, it connects the memory to the processor buses and I/O channels.
There are eight ports for
agents
for CPUs and I/O — each agent connects to two or four CPUs and one I/O channel —, and eight ports for memory. Each crossbar port has a data path of 64-bit, giving it 960 MB/s peak bandwidth. The peak bandwidth of the HyperPlane crossbar/ERACs is 15.3 GB/s combined. - Eight Exemplar Processor Agent controllers EPACs attach to the crossbar and provide access for each two processors Runway buses and one I/O controller to the memory via the crossbar over a 1.9 GB/s datapath, four 32-bit, unidirectional buses from two ports on the PAC connect to two Hyperplane crossbar ERACs; each EPAC thus communicates with only two of the system’s four ERACs. The I/O channels on the agents have a maximum bandwidth of either 120 or 240 MB/s. Each EPAC has two Runway processors buses, 64-bit, bidirectional, which have an aggregate peak bandwidth of 960 MB/s for two processors per EPAC.
- Eight Exemplar PCI-bus Interface controller EPICs connect the 240 MB/s I/O channels/PCI buses to the EPACs.
- Eight Exemplar Memory Access controllers EMACs attach each one 32-way interleaved memory board to the Hyperplane crossbar. Each EMAC has a bandwidth of 1.9 GB/s, four 32-bit, unidirectional buses from two ports on the EMAC connect to two Hyperplane crossbar ERACs.
- The Exemplar Core Utilities board ECUB provides interrupts and the central system logic, it connects to the Exemplar system Routing board ENRB. The Core Logic Bus from the ECUB attaches to the devices on the EPACs. Included on the ECUB are two custom FPGAs, the Exemplar Processor Utilities controller EPUC and the Exemplar Monitoring Utilities controller EMUC.
» View a system-level ASCII illustration of the crossbar architecture.
The remainder of the system I/O consist of standard HP PCI controllers, frequently:
- PCI Fast-wide FWD SCSI controller, high-voltage differential/HVD)
- PCI fibrechannel FC controller
System buses
- Total crossbar bandwidth 15.3 GB/s, intra-crossbar
- CPU bandwidth 7.5 GB/s, CPU-to-EPAC, eight Runway 960 MB/s buses
- Memory bandwidth 15 GB/s, memory-to-crossbar, sixteen 960 MB/s links
- I/O bandwidth 1.9 GB/s, eight 240 MB/s channels, I/O channel-to-EPAC
- Eight PCI-64/33 I/O buses for expansion slots, each 240 MB/s
- SCSI/storage buses depend on the installed SCSI adapter
Memory
- SDRAM DIMMs
- Two to eight memory boards, each memory board has 16 slots
- Memory is up to 32-way interleaved
- 16 GB maximum
Expansion slots
- 24 PCI 64-bit 33 MHz slots on eight PCI 64-bit channels
Storage
- 16 internal SCSI drives, exact type depending on installed SCSI adapter
External I/O
- External SCSI connection
- Serial and two Ethernet for the console/Teststation
Operating systems
Benchmarks
| Model | SPEC95 int |
SPEC95 fp |
SPEC95 rate, int |
SPEC95 rate, fp |
|---|---|---|---|---|
| V2200 | 13.8 | 22.1 | 1-CPU: 125 4-CPU: 484 8-CPU: 964 12-CPU: 1442 16-CPU: 1865 |
1-CPU: 4-CPU: 755 8-CPU: 1380 12-CPU: 1909 16-CPU: 2312 |
| V2250 | 16.4 | 24.8 | 16-CPU: 2209 | 16-CPU: 2471 |
Dimensions
| Height | Width | Depth | Weight |
|---|---|---|---|
| 1006mm | 998mm | 859mm | 250kg |
References
- Site Preparation Guide: HP 9000 V-Class Server Hewlett-Packard Development Company (March 1998, second edition, A3725-96021)
- Upgrade Guide HP V2200 to V2250 (PDF) Hewlett-Packard Company (March 1998, edition 1, A5083-90001)
- Architecture HP 9000 V-Class Server (PDF) Hewlett-Packard Company (March 1998, second edition, A3725-96022)