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HP 9000 V2200 and V2250

HP 9000 V2250 and V2250 are large-scale scalable PA-RISC servers, with up to sixteen 64-bit PA-RISC processors in a single cabinet. The architecture is a direct continuation from the Convex Exemplar. V2200 and V2250 use HP’s own HyperPlane crossbar chipset, consisting of four central crossbar ASICs and various other chipset components to attach memory, processors and I/O.

V2200/V2250 use a very similar crossbar-based system design to 64-bit SPP2000 S-Class/X-Class, minus the SCI/TCI links for interconnecting several nodes into a larger system. Their V2500/V2600 successors were delivered again with interconnection technology.

V2200 and V2250 are controlled via so-called teststations with its own HP-UX operating system to control and monitor V-Class servers. This teststation is a standard HP 9000/712 workstation with special teststation hardware such as a second ethernet and serial boards and software. The teststation connects to the Core Utilities Board (CUB), which provides booting, system monitoring and diagnostics, and console connections via one LAN and one special serial link.

• HP 9000 V2200 were introduced in 1997 for $157,000
• HP 9000 V2250 were introduced in 1998

Architecture

Processors

Chipset

1. HP HyperPlane 8x8 crossbar, non-blocking, four Exemplar Routing Attachment controllers (ERACs), the central part of the system connects memory to processor buses and I/O channels. Eight ports for CPUs and I/O agents, each connects to two or four CPUs and one I/O channel, and eight ports for memory.
2. Eight Exemplar Processor Agent controllers (EPACs) attach processors to the crossbar and provide access for each two processors Runway buses and one I/O controller to memory via the crossbar. Each EPAC communicates with two ERACs.
3. Eight Exemplar PCI-bus Interface controller (EPICs) connect I/O channels and PCI buses to the EPACs.
4. Eight Exemplar Memory Access controllers (EMACs) attach each an interleaved memory board to the Hyperplane crossbar.
5. Exemplar Core Utilities board (ECUB) provides interrupts and the central system logic, it connects to the Exemplar system Routing board ENRB. The Core Logic Bus from the ECUB attaches to the devices on the EPACs. Included on the ECUB are two custom FPGAs, the Exemplar Processor Utilities controller EPUC and the Exemplar Monitoring Utilities controller EMUC.

     (CPU1-2 aggregate 960MB/s)          
        //
       //   _____            _______            _____     ______
 CPU1----\_|     |          |       |          |     |   |Memory|
          _|EPAC1|  1.9GB/s | Cross | 1.9GB/s  |EMAC1|---|Board1|
 CPU2----/ |_____|==========|  bar  |==========|_____|   |______|
              |             | ERAC  |           
             I/O            |       |          
          120-240MB/s       | Hyper |         
              |             | Plane |        
             PCI1           |       |
                              15.3
              .             .  GB/s .            .          .
              .             .       .            .          .
              .             .       .            .          .
              .             .       .            .          .

            _____                               _____     ______
 CPU15---\_|     |          |       |          |     |   |Memory|
          _|EPAC8|  1.9GB/s |       | 1.9GB/s  |EMAC8|---|Board8|
 CPU16---/ |_____|==========|       |==========|_____|   |______|
              |             |       |          
             I/O            |       |         
          120-240MB/s       |       |        
              |             |       |       
             PCI8           |_______|

The remainder of the system I/O consist of standard HP PCI controllers:

• PCI Fast-wide FWD SCSI controller, high-voltage differential/HVD)
• PCI fibrechannel FC controller

System buses

• Total crossbar bandwidth 15.3 GB/s, intra-crossbar
  • Each crossbar port has a data path of 64-bit, giving it 960 MB/s peak bandwidth.
  • The peak bandwidth of the HyperPlane crossbar/ERACs is 15.3 GB/s combined.
• CPU bandwidth 7.5 GB/s, CPU-to-EPAC, eight Runway 960 MB/s buses
• Memory bandwidth 15 GB/s, memory-to-crossbar, sixteen 960 MB/s links
  • Each EMAC has a bandwidth of 1.9 GB/s for four 32-bit, unidirectional buses from two ports on the EMAC to two Hyperplane crossbar ERACs.
• I/O bandwidth 1.9 GB/s, eight 240 MB/s channels, I/O channel-to-EPAC
• Eight PCI-64/33 I/O buses for expansion slots, each 240 MB/s
• SCSI/storage buses depend on the installed SCSI adapter

Expansion

Memory

• Two to eight memory boards, each memory board has 16 slots
• SDRAM DIMMs
• Memory is up to 32-way interleaved
• 16 GB maximum

I/O slots

• 24 PCI 64-bit 33 MHz slots on eight PCI 64-bit channels

Storage

• 16 internal SCSI drives, exact type depending on installed SCSI adapter

I/O ports

• External SCSI connection
• Serial and two Ethernet for the console/Teststation

Operating systems

• HP-UX, the original HP Unix shipped with it
  • HP-UX 11i v1 in 64-bit mode, in EOE, FOE, MCOE versions (December 2000 December 2006)
  • HP-UX 11.00 in 64-bit mode

Benchmarks

Comparison to SPEC benchmark data from other Unix workstations and servers:

Dimensions

Documentation

• Site Preparation Guide: HP 9000 V-Class Server Hewlett-Packard Development Company (March 1998, second edition, A3725-96021) parisc linux
• Upgrade Guide HP V2200 to V2250 (PDF) Hewlett-Packard Company (March 1998, edition 1, A5083-90001) parisc linux
• Architecture HP 9000 V-Class Server (PDF) Hewlett-Packard Company (March 1998, second edition, A3725-96022) parisc linux
• HP Exemplar Technical Servers, Hewlett-Packard Company (1997: mirror accessed January 2024) archive.org

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OpenPA is an independent resource on PA-RISC computers, technology and operating systems, edited since 1999 by Paul Weissmann. He also publishes OpenKRITIS on critical infrastructures and Insel Westberlin, a Berlin archive. OpenPA is a registered serial publication, ISSN 1866-2757.

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