PA-RISC information - since 1999

HP 9000 V2500 and V2600

Quick Facts
Introduced 1998-1999
Period Maturity (III)
Series Mainframe
CPU 2-32 PA-8500 (V2500)
2-32 PA-8600 (V2600)
440-552 MHz
Caches 1.5 MB L1
Design HyperPlane
Drives 16 SCSI
Expansion 28 PCI
Bandwidth CPU 7.5 GB/s
Mem 15 GB/s
I/O 1.9 GB/s
XBAR 15.3 GB/s
SCI 3.8 GB/s
SCI (CTI/SCA) links

The HP 9000 V2500 and V2600 are scalable PA-RISC V-Class servers based on the Convex Exemplar architecture with up to 32 64-bit PA-RISC processors in a single cabinet. Up to four systems can be interconnected via CTI to form a combined system of up to 128 CPUs – appearing to the operating system as a single computer. The interconnected V2500s/V2500s are ccNUMA computers, as are the earlier HP 9000 V2200.

© Hewlett Packard 2000

The V-Class servers are based on a crossbar — one central internal switch links computing resources to each other by forming matrix connections. The V2500 and V2600 use HP’s own HyperPlane crossbar chipset, consisting of four central crossbar ASICs and various other chipset components to attach memory, processors and I/O.

The architecture is a direct continuation from the Convex Exemplar in the HP/Convex SPP1x00 and SPP2000 S-Class and X-Class, which used a similar crossbar system design based on GaA chips. This was upgraded for the V-Class with faster processors and memory. A multi-node V2500/V2600 system architecture (SCA) does not conform fully to PA-RISC 2.0 reference architecture – the firmware layer emulates a reference-compliant PA-RISC system for the operating system. However several changes had to be made to the HP-UX kernel to accomodate the V-Class’s special architecture, also called technical anomalies.

The V2500s and V2600s are controlled via a teststation, also called SSP, Service Support Processor, that runs its own operating system and controls and monitors the V-Class server, a a HP 9000/712 or B180L workstation. Earlier Convex systems apparently used IBM RS/6000 workstations running AIX to control the Exemplar systems. The SSP/teststation connects to the Core Utilities Board CUB, which provides booting, system monitoring and diagnostics, and console connections, connected via one LAN and one special serial link.

System architecture


Model CPU Speed L1 Cache
V2500 2-32 PA-8500 440 MHz 512/1024 KB on-chip
V26000 2-32 PA-8500 552 MHz 512/1024 KB on-chip


The V-Class V2500 and V2600 are based on the HP HyperPlane crossbar which connects the CPU and I/O to the system main memory.

  1. HyperPlane crossbar, 8x8, non-blocking, consists of four Routing Attachment controllers RACs and is the central part of the system, it connects the memory to the processor buses and I/O channels. There are eight ports for agents for CPUs and I/O — each agent connects to two or four CPUs and one I/O channel —, and eight ports for memory. Each crossbar port has a path width of 64-bit, giving it 960 MB/s peak bandwidth. The peak bandwidth of the HyperPlane crossbar/RACs is 15.3 GB/s combined.
  2. Eight Processor Agent controllers (PACs), also SPAC, attach to the crossbar and provide access for the processor Runway buses and I/O controllers to the memory via the crossbar over a 1.9 GB/s datapath, four 32-bit, unidirectional buses from two ports on the PAC connect to two Hyperplane crossbar RACs; each PAC thus communicates with only two of the system’s four RACs. The I/O channels on the agent have a maximum bandwidth of 240 MB/s. Each PAC has two Runway processors buses with an aggregate peak bandwidth of 960 MB/s.
  3. Eight PCI-bus Interface controller (SAGA) connect the 240 MB/s I/O channels/PCI buses to the PACs.
  4. Eight Memory Access controllers (MACs), also SMAC, attach each one 32-way interleaved memory board to the Hyperplane crossbar. Each MAC has a bandwidth of 1.9 GB/s, four 32-bit, unidirectional buses from two ports on the MAC connect to two Hyperplane crossbar RACs
  5. The Core Utilities board (CUB) provides interrupts and the central system logic, it connects to the Midplane Interconnect Board MIB. The Core Logic Bus from the CUB attaches to the devices on the PACs.
  6. Eight Toroidal Access Controller (STACs) connect to a variation of the Scalable Coherent Interconnect SCI to one or two rings. The combination of STACs and SCI rings is referred to as Coherent Toroidal Interconnect CTI.

» View a system-level ASCII illustration of the crossbar architecture.

The remainder of the system I/O consist of standard HP PCI controllers, frequently shipped in default configuration with one of the following:

System buses


Expansion slots



Multiple V-Classes can be connected together to form a single large system resulting in a SCA, a scalable Computing Architecture system. Up two four V2500/V2600s can be clustered together to form a system with up to 128 processors, 128 GB of RAM, 112 PCI slots and 64 SCSI drives. Clustered V-Classes are ccNUMA computers and do not conform fully to the PA-RISC 2.0 specification.

Multiple systems are connected via two CTI rings: these links attach via the STACs to the eight memory controllers. The two rings are called X-ring and Y-ring. Each system attaches to one or two other V2500/V2600 cabinets and their respective crossbars with a node-to-note data rate of 3.8 GB/s. The links are implementation of the IEEE SCI standard taken over from Convex — Coherent Toroidal Interconnect or Convex Toroidal Interconnect. Each node’s main memory is globally accessible from other nodes on the CTI network, that is, local memory is globally shared. 32-512 MB of each system’s main memory is reserved for cache memory for the CTI network configured statically at boot time.

External ports

Operating systems


Model SPEC95
rate, int
V2500 16-CPU: 4002
32-CPU: 7481
V2600 16-CPU: 5164
32-CPU: 9315


Height Width Depth Weight
990mm 800mm 940mm 223kg




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