PA-RISC information - since 1999

HP 9000 V2500 and V2600

Quick Facts
Introduced 1998-1999
Period Maturity (III)
Series Mainframe
CPU 2-32 PA-8500 (V2500)
2-32 PA-8600 (V2600)
440-552 MHz
Caches 1.5 MB L1
RAM 32 GB
Design HyperPlane
Drives 16 SCSI
Expansion 28 PCI
I/O SCSI
Console
SCI (CTI/SCA) links

HP 9000 V2500 and V2600 are scalable PA-RISC V-Class servers based on Convex Exemplar architecture with up to 32 64-bit PA-RISC processors in a single cabinet. Up to four systems can be interconnected via CTI to form a combined system of up to 128 CPUs – a single computer to the operating system. Interconnected V2500s/V2500s are ccNUMA computers.

© Hewlett Packard 2000

V-Class servers are based on a crossbar, a central internal switch that links computing resources to each other by forming matrix connections. V2500 and V2600 use HP HyperPlane chipset with four central ASICs and other components to attach memory, processors and I/O.

The architecture is a direct continuation of Convex Exemplar, used in HP Convex SPP1x00 and SPP2000 S-Class and X-Class in a similar crossbar design with GaA chips. This was upgraded for V-Class with faster processors and memory. A multi-node V2500/V2600 system architecture (SCA) does not conform fully to PA-RISC 2.0 reference architecture – the firmware layer emulates a reference-compliant PA-RISC system for the operating system. Several changes had to be made to the HP-UX kernel to accomodate the V-Class’s special architecture.

V2500 and V2600 are controlled via a teststation, also called SSP, Service Support Processor, that runs its own operating system and controls and monitors the V-Class server, a a HP 9000/712 or B180L workstation. The SSP/teststation connects to the Core Utilities Board (CUB) for booting, system monitoring and diagnostics, console connections, connected via one LAN and one special serial link.

System architecture

Processors

System CPU Speed L1 cache
HP 9000 V2500 2-32 PA-8500 PA-RISC 64-bit 440 MHz 512/1024 KB on-chip
HP 9000 V26000 2-32 PA-8500 PA-RISC 64-bit 552 MHz 512/1024 KB on-chip

Chipset

  1. HP HyperPlane 8x8 crossbar, non-blocking, four Exemplar Routing Attachment controllers (ERACs), the central part of the system connects memory to processor buses and I/O channels. Eight ports for CPUs and I/O agents, each connects to two or four CPUs and one I/O channel, and eight ports for memory.
  2. Eight Processor Agent controllers (PAC, also SPAC), attach processors to the crossbar and provide access for processor Runway buses and I/O controllers to the memory via the crossbar; each PAC communicates with two RACs.
  3. Eight PCI-bus Interface controller (SAGA) connect I/O channels and PCI buses to the PACs.
  4. Eight Memory Access controllers (MAC, also SMAC), attach an interleaved memory board to the Hyperplane crossbar.
  5. The Core Utilities board (CUB) provides interrupts and the central system logic, it connects to the Midplane Interconnect Board MIB. The Core Logic Bus from the CUB attaches to the devices on the PACs.
  6. Eight Toroidal Access Controller (STACs) connect to a variation of the Scalable Coherent Interconnect SCI to one or two rings. The combination of STACs and SCI rings is referred to as Coherent Toroidal Interconnect CTI.

» View a system-level ASCII illustration of the crossbar architecture.

The remainder of the system I/O consist of standard HP PCI controllers, frequently shipped in default configuration with one of the following:

System buses

Memory

Expansion slots

Storage

Clustering

Multiple V-Classes can be connected together to form a single large system resulting in a SCA, a scalable Computing Architecture system. Up two four V2500/V2600s can be clustered together to form a system with up to 128 processors, 128 GB of RAM, 112 PCI slots and 64 SCSI drives. Clustered V-Classes are ccNUMA computers and do not conform fully to the PA-RISC 2.0 specification.

Multiple systems are connected via two CTI rings: these links attach via the STACs to the eight memory controllers. The two rings are called X-ring and Y-ring. Each system attaches to one or two other V2500/V2600 cabinets and their respective crossbars with a node-to-note data rate of 3.8 GB/s. The links are implementation of the IEEE SCI standard taken over from Convex — Coherent Toroidal Interconnect or Convex Toroidal Interconnect. Each node’s main memory is globally accessible from other nodes on the CTI network, that is, local memory is globally shared. 32-512 MB of each system’s main memory is reserved for cache memory for the CTI network configured statically at boot time.

External ports

Operating systems

Benchmarks

System SPEC95
rate int		 SPEC95
rate fp
V2500 16-CPU: 4002
32-CPU: 7481
V2600 16-CPU: 5164
32-CPU: 9315

Comparison to SPEC benchmark data from other Unix workstations and servers:

Based on old SPEC95rate archives
System Processor SPEC92
fp		 SPEC95
int		 SPEC95
fp		 SPEC95
rate int		 SPEC95
rate fp
DG AViiON AV 20000 16-CPU Pentium Pro 200 MHz 1007
DEC AlphaServer 8400 5/300 12-CPU 21164 300 MHz 33 (8P) 767 919
Siemens RM600 720 24-CPU R4400 250 MHz 921
HP 9000 D380 2-CPU PA-8000 180 MHz 12 17 210 221
HP 9000 K580 6-CPU PA-8200 240 MHz 17 (1P) 28 (1P) 902 849
HP 9000 T600 12-CPU PA-8000 180 MHz 12 15 1192 1151
Convex SPP1600 8-CPU PA-7200 120 MHz
16-CPU PA-7200 120 MHz
32-CPU PA-7200 120 MHz		 290
541
996		 383
744
1444
Convex SPP20000 8-CPU PA-8000 180 MHz
16-CPU PA-8000 180 MHz		 713
1307		 935
1413
HP Visualize C3600 1-CPU PA-8600 552 MHz 42 64 379 576

Dimensions

Height Width Depth Weight
990mm 800mm 940mm 223kg

Documentation

Manuals

Articles

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