HP Convex SPP2000 S-Class, X-Class
| Quick Facts | |
|---|---|
| Introduced | 1997 |
| Period | Maturity (III) |
| Series | Mainframe |
| CPU | 4-16 64-bit PA-8000 180 MHz |
| Caches | 1/1 MB L1 |
| RAM | 16 GB |
| Design | Crossbar |
| Drives | 20 SCSI |
| Expansion | 28 PCI |
| I/O | SCSI Console SCI (CTI) |
Convex Exemplar SPP2000 and SP2200 are large, scalable 64-bit PA-RISC servers based on Convex Exemplar technology, integrated into HP’s lineup after the acquisition of Convex. HP named them S-Class and X-Class as the predecessors of later HP 9000 V-Class V2200 and V2500 servers.
Developed based on Convex Exemplar SPP1000 technology, HP SPP2000 and S-Class use a similar crossbar architecture.
This crossbar uses central internal switching
to connect resources to each other by forming matrix connections between input and output ports.
A single SPP2000 can hold up to sixteen 64-bit PA-8000 processors with 16 GB memory in a single Node, called S-Class.
SPP2000s can form large-scale systems by connecting single nodes with SCI links into larger clusters of up to 32 nodes and 512 processors. The resulting system is called X-Class, ccNUMA computers. The clustering capabilities of their successors, the V2500, were reduced significantly — in contrast to the 32-node maximum of SPP2000 clusters, V2500s only can be clustered into groups of four.
SPP2000/S-Class were operated and controlled via so-called teststations,
Unix workstations that connect to a central management board in single nodes which provides booting, system monitoring and diagnostics and console.
Teststations were either IBM RS/6000 AIX systems or more commonly HP 9000 workstation running HP-UX.
- SPP2000 S-Class were introduced in 1997, with 4 CPUs for $189,000
- SPP2000 X-Class were introduced in 1997, with 16 CPUs for $720,000
- SPP2000 X-Class were introduced in 1997, with 64 CPUs for $3 million
System
Processors
| System | Type | CPU | Speed | L1 Cache | |
|---|---|---|---|---|---|
| SPP2000 S-Class | Node | 4-16 | PA-8000 PA-RISC 64-bit | 180 MHz | 1/1 MB off-chip |
| SPP2000 X-Class | Cluster/Wall | 32-512 | PA-8000 PA-RISC 64-bit | 180 MHz | 1/1 MB off-chip |
| SPP2200 X-Class | Cluster/Wall | 32-512 | PA-8200 PA-RISC 64-bit | 200 MHz | 1/1 MB off-chip |
Chipset
SPP2000 are based on Exemplar crossbar architecture which connects CPU and I/O to system main memory.
- 8x8 nonblocking crossbar, the central part of an Exemplar, connects memory to processor buses and I/O channels. Eight ports for agents connect to each two CPUs and one I/O channel, and eight ports for memory. Each port has 64-bit 960 MB/s bandwidth, combined 15.3 GB/s for the crossbar, built in CMOS with 1.1M transistors (GaA in SPP1x00 Exemplar).
- Eight Data Mover/Agents attach to the crossbar and provide access for the processors with Runway buses and I/O controllers to the memory via the crossbar over a 1.9 GB/s datapath with four 32-bit, unidirectional buses from two ports on the Agent connect to two crossbar ports. The I/O channels on the agent have a maximum bandwidth of 240 MB/s. Each Agent has two Runway processors buses with an aggregate bandwidth of 960 MB/s.
- Eight PCI controller connect 240 MB/s I/O channels/PCI buses to agents.
- Eight Memory controllers attach each one four-way interleaved memory board to the Hyperplane crossbar. Each memory controller has a bandwidth of 1.9 GB/s.
(CPU1-2 aggregate 960MB/s)
//
// ______ _______ ________ ______
CPU1----\_|Agent1| | | | | |Memory|
_|Data | 1.9GB/s| Cross | 1.9GB/s |Memory |---|Board1|
CPU2----/ |Mover |========| bar |==========|Control1| |______|
|______| | | |________|
| | | | |
| | | | |
240MB/s | 15.3 | SCI SCI
| | GB/s | X-Ring Y-Ring
PCI1 | |
. . . . .
. . . . .
. . . . .
______ ________ ______
CPU15---\_|Agent8| | | | | |Memory|
_|Data | 1.9GB/s| Cross | 1.9GB/s |Memory |---|Board8|
CPU16---/ |Mover |========| bar |==========|Control8| |______|
|______| | | |________|
| | | | |
| | | | |
240MB/s | | SCI SCI
| |_______| X-Ring Y-Ring
PCI8
Convex SPP2000 Crossbar Architecture System Architecture
System buses
- Total crossbar bandwidth 15.3 GB/s (intra-crossbar)
- CPU bandwidth 7.5 GB/s (CPU-to-Agent, eight Runway 960 MB/s buses)
- Memory bandwidth 15 GB/s (memory-to-crossbar, sixteen 960 MB/s links)
- I/O bandwidth 1.9 GB/s (eight 240 MB/s channels, I/O channel-to-Agent)
- Eight PCI-32 I/O buses for expansion slots (each 240 MB/s)
- Attachments to SCI rings/CTI (
Coherent Toroidal Interconnect
) via two rings (X-ring and Y-ring), Node-to-Node bandwidth of 3.84 GB/s, the rings operate at a clock of 120 MHz with a width of 32 bit - SCSI-2 Ultra main storage I/O bus
Expansion
Memory
- SDRAM DIMMs
- Two to eight memory boards per node
- Memory is up to four-way interleaved per memory board and up to 32-way interleaved per node
- SPP2000 Node/S-Class: 1 GB minimum, 16 GB maximum
- SPP2000 Wall/X-Class: 512 GB maximum (with 32 nodes)
Expansion cards
- 24 PCI 32-bit slots on eight PCI 32-bit channels
Storage
- 20 internal Ultra SCSI drives
I/O ports
- 68-pin VHDCI Ultra LVD external SCSI
- Three serial RS232C DB9 (local & remote console, general purpose) via DB25
M cable
- 10/100 Mbit Ethernet TP/RJ45
- 10/100 Mbit Ethernet TP/RJ45 LAN console
Clustering
Multiple Exemplar SPP2000/HP S-Class systems can be connected together to form a single large system,
a Wall
/X-Class.
- Up two 32 single nodes can be clustered together to form a system with up to
- 512 processors
- 512 GB of RAM
- 768 PCI slots
- 640 SCSI drives
- Clustered SPP2000s/X-Class are ccNUMA computers; they are not fully conformant to the PA-RISC 2.0 specification (and thus do not run standard HP-UX).
- Multiple systems are connected via two CTI rings: these links attach
to the eight memory controllers of a node.
A single system attaches to other single
nodes
and their respective crossbars with a node-to-note data rate of 3.8 GB/s. - The two rings are called X-ring and Y-ring.
- The links are implementations of the IEEE SCI from Convex — Convex Toroidal Interconnect.
- Each node’s main memory is globally accessible from other nodes on the CTI network (that is, local memory is globally shared).
- A part of each system’s main memory is reserved for cache memory for the CTI network (configured statically at boot time).
Operating systems
Convex SPP Exemplar with PA-RISC processors exclusively run SPP-UX, a scalable Unix based on Mach, developed by Convex for SPP1000 and SPP2000 mainframes with up to 512 processors, released between 1993 and 1999. SPP-UX implemented a distributed architecture that emulated HP-UX for developers but was very different below the userland.
Performance
Convex SPP Exemplar were impressive but expensive scalar RISC servers, the second generation much faster than other RISC architectures like UltraSPARC, MIPS and Intel. Convex with PA-RISC Exemplar technology competed on floating-point use cases (MFLOPS) with supercomputers, a long Convex tradition.
| System | Processor | SPEC95 rate int/fp |
Linpack TPP Rmax |
||
|---|---|---|---|---|---|
| SPP2000 S-Class X-Class |
1 PA-8000 180 MHz 2 PA-8000 180 MHz 4 PA-8000 180 MHz 6 PA-8000 180 MHz 8 PA-8000 180 MHz 12 PA-8000 180 MHz 16 PA-8000 180 MHz 32 PA-8000 180 MHz 64 PA-8000 180 MHz |
92.5 183 363 539 713 1012 1307 |
141 276 524 739 935 1220 1413 6140 |
545 967 1629 2305 2979 4019 4609 |
2.12 4.10 6.01 7.78 15.01 27.56 |
| System | Processor | SPEC95 rate int/fp |
Linpack TPP Rmax |
||
|---|---|---|---|---|---|
| Cray T90 T932 | 32 Cray ECL 450 MHz | 29360 | 61.80 | ||
| HP 9000 V2500 | 32 PA-8500 440 MHz 16 PA-8500 440 MHz |
7481 | 8217 |
31.59 17.47 |
|
| AlphaServer HPC320 AlphaServer HPC160 |
32 Alpha 21264 500 MHz 16 Alpha 21264 500 MHz |
7264 3837 |
11779 6246 |
||
| Cray SV1 | 24 Cray CMOS 300 MHz | 10420 | 38.31 | ||
| AlphaServer 8400 | 32 Alpha 21164 625 MHz 8 Alpha 21164 625 MHz |
4504 1279 |
4527 1212 |
3608 |
17.96 |
| Sun Starfire | 32 Sun UltraSPARC-II 333 | 3480 | 3021 | 5187 | 17.91 |
| SGI Origin 2000 | 16 R12000 300 MHz | 2560 | 4224 | 3970 | 8.71 |
| HP V2250 | 16 PA-8200 240 MHz | 2209 | 2471 | 5935 | 10.65 |
| HP V2200 | 16 PA-8200 200 MHz | 1865 | 2312 | 4832 | 9.20 |
| Sun Enterprise 6k | 16 Sun UltraSPARC 250 | 1437 | 1965 | 3493 | 7.21 |
| Convex SPP1000 | 64 PA-7100 100 MHz 8 PA-7100 100 MHz |
751 |
6.19 |
||
| AlphaServer ES40 | 4 Alpha 21264 667 MHz | 1390 | 2686 | 3804 | 4.11 |
| HP 9000 T600 | 12 PA-8000 180 MHz | 1192 | 1151 | ||
| DG AViiON AV 20000 | 16 Pentium Pro 200 MHz | 1007 | |||
| Convex SPP1600 | 32 PA-7200 120 MHz | 996 | 1444 | 5.45 | |
| Siemens RM600 720 | 24 R4400 250 MHz | 921 | |||
| HP 9000 K580 | 6 PA-8200 240 MHz | 902 | 849 | ||
| IBM RS/6000 SP | 4 POWER3 375 MHz | 845 | 1739 | 3700 | 4.64 |
| Convex SPP1200 | 32 PA-7200 120 MHz 8 PA-7200 120 MHz |
656 |
3.96 1.02 |
||
| HP Visualize C3600 | 1 PA-8600 552 MHz | 379 | 576 | ||
| Cray C90 | 1 Cray 238 MHz | 902 | 2.92 | ||
Dimensions
| Height | Width | Depth | Weight |
|---|---|---|---|
| 736mm | 914mm | 889mm | 250kg |
Documentation
Most HP and Convex documentation is only available at archive.org and other archives, with most official sources, articles and journals having disappeared in the 2010s.
- Exemplar System Architecture Hewlett-Packard/Convex (Januar 1997, accessed August 2008) archive.org
- SPP 2000 Architecture presentation (Postscript) Beth Richardson (N.d.: NCSA. Google archive accessed August 2008)
- A Comparative Evaluation of Hierarchical Network Architecture of the HP-Convex Exemplar (Postscript) Robert Castaneda, et al. (1997: in Proceedings of IEEE International Conference on Computer Design (ICCD’97) [there is a mirrored PDF version from citeseer (accessed August 2008)]
- Convex Division Data Sheets Hewlett-Packard Convex, October 1996 archive.org
- New PA-8000 Scalable Systems from HP Redefine Price/Performance in Technical-server Computing Hewlett-Packard 1996 archive.org
